1. Field of the Invention
The present invention relates generally to a bipolar transistor to be employed in an integrated circuit for driving an EL display, a plasma display and the like. More specifically, the invention relates to a insulated gate type bipolar transistor having high tolerance voltage which can be formed together with a low voltage control circuit on a single semiconductor substrate.
2. Description of the Prior Art
In the conventional integrated circuit for driving an EL display and a plasma display, a low voltage type CMOS logic circuit which has operation voltage about 5V, is employed at an input side, and N-channel type insulated gate type field effect transistor, for example is employed at an output side.
FIG. 1 is a section showing a structure of an output transistor in the conventional integrated circuit for driving the EL display. This will be referred to hereinafter as "first prior art". Field insulation layers 21 are selectively formed at a surface of a P-type semiconductor substrate 1. By this, device regions are defined in the semiconductor substrate. Thermal oxidation layers 2 serving as a gate oxide layer are selectively formed on the surface of the device region in a thickness thinner than that of the field insulation layers 21. Stripe form gate electrodes 3 are formed in a region extending over the thermal oxidation layers 2 and the field insulation layers 21.
Also, at the surface of the P-type semiconductor substrate 1 at the device region side where the thermal oxidation layer 2 is not formed, in a region extending over the adjacent field insulation layer 21, an N-type drain well diffusion layer 4 and an N-type extended drain diffusion layer 5, which has a depth shallower than and an area wider than the N-type drain well diffusion layer 4, are formed. An extended drain type drain diffusion layer having high tolerance voltage is formed by the drain well diffusion layer 4 and the extended drain diffusion layer 5. An N-type high concentration drain layer 13 with a depth shallower than that of the N-type extended drain diffusion layer 5 and having higher concentration than the latter is formed at the surface of the center portion of the drain diffusion layer.
An N-type source diffusion layer 7 is formed at the surface of the P-type semiconductor substrate 1 in the device region side where the thermal oxidation layer 2 is formed, and a P-type substrate contact layer 8 is formed adjacent the source diffusion layer 7. The P-type substrate contact layer 8 is contacted with the N-type source diffusion layer 7 and is distanced from a gate electrode 3 in greater distance than that of the N-type source diffusion layer 7.
A surface insulation layer 11 is formed over the entire surface. The surface insulation layer 11 provided with contact holes in regions aligning with the center portions of respective device regions. A drain terminal 15 is formed on the surface of the N-type high concentration drain layer 13 exposed by formation of the contact hole. Also, source terminals 14 are formed on the surfaces of the N-type source diffusion layer 7 and the P-type substrate contact layer 8 exposed by formation of the contact holes.
An insulated gate field effect transistor of normally horizontal structure is employed at the output side in the conventional integrated circuit for driving the EL display. This is because that the field effect transistor shown in FIG. 1 is easy to fabricate and is suitable for circuit construction with the low-voltage type control circuit formed at the input side.
As a transistor which can be formed together with the low-voltage type control circuit on a common semiconductor substrate, there is an insulated gate type bipolar transistor having a structure different from that of the first prior art. This will be referred to as "second prior art". FIG. 2 is a section showing a structure of the insulation gate type bipolar transistor of the second prior art. In the second prior art, like elements to those in the first prior art shown in FIG. 1 will be identified by like reference numerals and detailed description therefor will be neglected for simplification of disclosure.
In the second prior art, an N-type epitaxial layer 16 is grown on the surface of the P-type semiconductor substrate 1. At the surface of the N-type epitaxial layer 16 at the device region side not formed the thermal oxidation layer 2, a P-type emitter diffusion layer 17 is formed on the region extending over the adjacent field insulation layer 21. The P-type emitter diffusion layer 17 is formed at a position distanced from the gate electrode in a distance range of 10 to several ten .mu.m.
On the other hand, a P-type base diffusion layer 19 is formed at the surface of the N-type epitaxial layer 16 at the device region side where the thermal oxidation layer 2 is formed. An N-type source diffusion layer 20 is formed at the surface of the center portion of the P-type base diffusion layer 19. A P-type insulation diffusion layer 18 contacting with the P-type base diffusion layer 19 at a position away from the gate electrode 3 is formed in a region extending from the surface of the N-type epitaxial layer 16 to the surface of the P-type semiconductor substrate 1.
Also, via the contact hole provided in the surface insulation layer 11, the P-type base diffusion layer 19 and the N-type source diffusion layer 20 are connected to have the same potential to lead out from the device as a collector terminal 10. Similarly, via the contact hole provided in the surface insulation layer 11, the emitter terminal 9 is lead out from the P-type emitter diffusion layer 17, and the gate terminal (not shown) is lead out from the gate electrode 3.
In the first prior art, there is no process step for significantly increasing fabrication cost, such as growth process of an epitaxial layer, forming process of insulation diffusion layer and so forth. Each diffusion layer is formed by only process of introducing impurity from the surface of the semiconductor substrate. Accordingly, in fabrication of the driving integrated circuit having a self-separation structure which is low in fabrication cost, a horizontal type insulation gate field effect transistor is typically selected as high rating voltage output transistor.
However, when the driving integrated circuit is fabricated with employing the insulation gate type field effect transistor of the first prior art, the following problem will be encountered. Namely, the driving integrated circuit typically has several tens or more in number of high rating voltage output transistors and corresponding output terminals in one circuit. Each output terminal is directly connected to corresponding scanning line electrode. The scanning line electrodes of the EL display and plasma display become loads of the driving integrated circuit. This load is capacity type having large charge amount and discharge amount, and the capacitance of each scanning line becomes several nF. As set forth, since the capacitance of the scanning line electrode is large, the rated value of the output current of the driving integrated circuit becomes several hundreds mA per one output which should be large current for the integrated circuit. In order to realize large rated current, since the gate width of the output transistor is formed to have large width, sixty to seventy percent of chip area is occupied by the output transistor.
On the other hand, when the output transistor is turned on, namely in transition from steady state at off state to steady state at on state, since the scanning line electrode to be the load is capacitance type, a variation trace (load line) between a drain voltage and a drain current of the output transistor becomes a trace close to a thermal breakdown point. Accordingly, it becomes necessary to certainly provide sufficient distance between the thermal breakdown point and the load line.
As a method to certainly provide sufficient distance between the thermal breakdown line and the load line, there is a method to restrict heat generation amount per unit area, in addition to the method for improving radiation efficiency. When heat generation amount per unit area is restricted, a problem to further increase the chip area is encountered.
In the recent years, increasing of screen size and increasing of display colors of the EL display and plasma display, the output rated current of the driving integrated circuit is increased. This should significantly increase the chip area.
On the other hand, the operation characteristics of the insulated gate type bipolar transistor of the second prior art, a current value may not be saturated even when the voltage is increased in the on state. Namely, the operation resistance is maintained low up to large current region, heat radiation within the transistor is small even in large current state. Also, a sufficient distance between the thermal breakdown point and the drain voltage - drain current trace (load line) upon transition from the steady state at off state to the steady state at on state, can be present. Accordingly, when the insulated gate type bipolar transistor is employed as the output transistor of the driving integrated circuit, the problem in the case where the first prior art has been generated is not encountered.
However, as set forth above, in order to form the insulated gate type bipolar transistor shown in FIG. 2, the fabrication process, such as growth of epitaxial layer and formation of the insulation diffusion layer and so forth, becomes necessary to cause significant increase of the fabrication cost.